1. Field of the Invention
The present invention relates to flash memory devices and more particularly, to a NAND-type flash memory device configured to prevent programming disturbance at memory cells adjacent to drain and source selection transistors and to improve programming speeds for memory cells.
2. Discussion of Related Art
Flash memories, which are known as types of nonvolatile memory devices capable of retaining data even when power is interrupted therein, are referred to as devices operable without refresh functions. In flash memories, “programming” refers to an operation for writing data in memory cells. “Erasing” refers to an operation for eliminating data from memory cells. Such flash memories are roughly classified into NOR and NAND types in accordance with the cell structures and operational conditions. A NOR-type flash memory, in which the sources of memory cell transistors are coupled to a ground voltage, can program erase data for memory cells with random addresses, and can be used in applications necessary for high operation speed. A NAND-type flash memory is configured with pluralities of memory cell transistors coupled in series to form a cell string that is connected between a drain selection transistor and a source selection transistor, which can be used for high-density data storage.
FIG. 1 shows a conventional NAND-type flash memory device.
Referring to FIG. 1, the number of memory cells MC0˜MC31 are coupled in series between a drain selection transistor DST and a source selection transistor SST. Typical designs involve 16, 32, or 64 memory cells in consideration with the device topology and density.
In FIG. 1, there are pluralities of cell strings each of which is composed of 32 memory cells. Memory cells (e.g., MC0) controlled by a single wordline (e.g., WL0) form one page that is a group of memory cells. FIG. 1 exemplarily shows 32 pages.
However, the NAND-type flash memory device as shown FIG. 1 is vulnerable to program disturbances arising from memory cells MC0, which are coupled to the first wordline WL0 adjacent to the source selection line SSL and a deselected bitline (e.g., BL0), and program disturbances from memory cells MC31 coupled to the last wordline adjacent to the drain selection line DSL and the deselected bitline BL0. These program disturbances occur because channels of the source selection transistor SST, the drain selection transistor DST, and the memory cells MC0˜MC31 are boosted up to 0V, 1V, and about 8V, respectively, when a ground voltage 0V, a power source voltage VCC, and a program inhibit voltage Vpass are applied to the source selection line SSL, the drain selection line DSL, and the rest wordlines WL1˜WL31, respectively.
In more detail, a lateral electric field is strongly formed between the source selection transistor SST and the memory cell MC0 due to the difference of channel voltages between source selection transistor SST and memory cell MC0, i.e., between 0V and 8V. A lateral electric field is also formed between the drain selection transistor DST and the memory cell MC31 due to the difference of channel voltages between drain selection transistor DST and memory cell MC31, i.e., between 1V and 8V. If such voltage differences causes the strong electric fields laterally, electrons generated at borders between a gate oxide film of the source selection transistor SST and a silicon substrate Si-Sub move toward the memory cell MC0 along the surface of the silicon substrate Si-Sub, resulting in hot electrons. Those hot electrons generated move in a lateral direction and flow into floating gates of the memory cells MC0 and MC31, programming the memory cells MC0 and MC31.
Meanwhile, programming speeds for the memory cells MC0 and MC31 coupled to a selected bitline BL1 and the first and last wordlines WL0 and WL31 are slower than those for other memory cells MC1˜MC30. The reason for the slower programming speeds is because threshold voltages Vt of the memory cells MC0 and MC31 coupled to the first and last wordlines WL0 and WL31 and the selected bitline BL1 are lower than threshold voltages of the memory cells MC1˜MC30 coupled to the rest of wordlines WL1˜WL30 so that there are voltage differences between the source selection line SSL and the first wordline WL0 and between the drain selection line DSL and the last wordline WL31.
In other words, the memory cells MC0 and MC31 are influenced by electric potentials of the source selection transistor SST and the drain selection transistor DST, so that the threshold voltages of the memory cells MC0 and MC31 become lower than those of the other memory cells MC1˜MC30. As a result, the memory cells MC0 and MC31 have slower programming speeds than that of the other memory cells MC1˜MC30.
FIG. 2 is a graphic diagram showing a wordline with program disturbance by hot electrons in the NAND-type flash memory device of FIG. 1, illustrating the relation between the memory cell MC0, MC31, and the program inhibit voltage Vpass.
As shown in FIG. 2, the memory cells MC0 and MC31 coupled to the first and last wordlines WL0 and WL31, respectively, have different threshold voltages Vt than that of the other memory cells MC1˜MC30 respectively coupled to the rest wordlines WL1˜WL30. This arises from the program disturbance by the hot electrons as aforementioned.
FIG. 3 is a graphic diagram showing distribution profiles of threshold voltages Vt of the memory cells MC0˜MC31 while performing a program operation with the same voltage to the wordlines WL0˜WL31 of the memory cells MC0˜MC31 coupled to the selected bitline BL1. Here, the lower threshold voltages result in slower programming speeds.
As shown in FIG. 3, it can be seen that the programming speed becomes slower due to the lower threshold voltages of the memory cells MC0 and MC31 coupled to the first and last wordlines WL0 and WL31, respectively, in comparison with those of the other memory cells WL1˜WL30.
The effect of program disturbance as shown in FIG. 2 and the degradation of programming speed as shown in FIG. 3 becomes more serious as a memory cell becomes smaller in size. And, a multi-level cell is more vulnerable against the aforementioned troubles than a single-level cell. As a result, such program disturbance and degradation of programming speed may deteriorate the performance of the NAND-type flash memory device.